1. Field of the Invention
The present invention generally relates to electronic circuits for generating clock signals, and more particularly to multiphase clock generators.
2. Description of Related Art
High-speed serial communication systems transmit and receive data in serial data streams. A serial data stream is a sequence of digital pulses that represents data as a sequence of binary values. A transmitter in the serial communication system uses a clock signal to encode data into a serial data stream and transmits the serial data stream to a receiver in the serial communication system. The receiver generates a clock signal having the same frequency as the clock signal in the transmitter and uses the clock signal to extract and reconstruct the data from the serial data stream.
Some receivers include a clock generator that extracts and reconstructs a clock signal from the serial data stream. The reconstructed clock signal has the same frequency as the clock signal used by transmitter to encode data into the serial data stream. In some receivers, the clock generator reconstructs a multiphase clock signal that includes in-phase clock signals and quadrature clock signals. The in-phase clock signals differ in phase by 180 degrees. The quadrature clock signals differ in phase by 180 degrees. Further, each of the quadrature clock signals differs in phase from each of the in-phase clock signals by 90 degrees. The clock generator aligns the phases of the in-phase clock signals to data transition points in the serial data stream and uses the quadrature clock signals to extract data between data transition points in the serial data stream.
In many high-speed communications systems, the clock generator of a receiver includes a phase interpolator for each of the in-phase and quadrature clock signals. The phase interpolator of each of the in-phase clock signals adjusts the phase of that clock signal to align the clock signal with data transition points in the serial data stream. The phase interpolator of each of the quadrature clock signals adjusts the phase of that clock signal to maintain its phase relationship with the in-phase clock signals. Although phase interpolators have been successfully used to adjust the phases of clock signals generated in a receiver, phase interpolators generally consume a considerable amount of power and area in those applications in which multiple phase interpolators are used. In particular, multiple phase interpolators consume a considerable amount of power and chip area in integrated circuit applications. Moreover, performance variations among multiple phase interpolators in a receiver tend to cause timing jitter between the phases of the clock signals generated by the phase interpolators. The timing jitter decreases the accuracy of the clock generator in maintaining the phase relationships of the generated clock signals, which decreases performance of the receiver.
In light of the above, a need exists for reducing power and area consumption of a multiphase clock generator. A further need exists for improving the accuracy of a multiphase clock generator.